1. Field of the Invention
The present invention relates generally to waveform drivers and, more particularly, to their use in pin electronics for automatic test equipment (ATE).
2. Description of the Related Art
An exemplary use of transistor waveform drivers can be found in the field of ATE where test waveforms are generated and applied to leads of devices under test (DUTs). Because these waveforms are typically applied via an ATE "pin" (i.e., a probe), circuits configured for this purpose are also referred to as "pin drivers" and comprise a more general class of support circuitry commonly referred to as ATE "pin electronics". Preferably, the magnitudes and baseline components of pin-driver waveforms can be individually adjusted over ranges that accommodate a variety of DUTs and, in addition, the waveforms should have fast, symmetric rising and falling edges with minimal transients. Because ATE systems typically employ a large number (e.g., 1024) of pin drivers, the drivers are preferably realized with simple, inexpensive circuits.
A first exemplary pin driver is shown in U.S. Pat. No. 4,572,971 to couple a level selector circuit to a DUT with a buffer circuit. The level selector circuit is arranged to accommodate reference voltages that represent both small and large voltage swings. In response to first and second reference voltages and a current switch, the level selector circuit generates a signal equal to a selected one of the reference voltages at an output node. The output node signals are applied to the DUT through a unity-gain buffer circuit having two stages that each comprise a complementary emitter follower.
A second exemplary pin driver is disclosed in U.S. Pat. No. 5,842,155 which couples a pulse forming circuit to a DUT with buffer and amplifier stages. The pulse forming network responds to high and low signal inputs by respectively charging and discharging a network node with currents of equal and opposite magnitudes so as to achieve pulses having equal positive and negative slew rates between pulse magnitudes equal to the high and low inputs. The pulses thus formed at the network node are then applied to the DUT through unity-gain buffer and amplifier stages which each comprise a complementary emitter follower structure.
Although these exemplary pin drivers can generate pulse signals with controlled amplitudes, they fail to provide for independent adjustment of a baseline component and are relatively complex (e.g., the pulse forming circuit and buffer and amplifier stages of U.S. Pat. No. 5,842,155 include 11 transistors and the components of U.S. Pat. No. 4,572,971 are even more numerous.
FIG. 1A shows another pin driver 5 that is formed with a buffer amplifier 6, a differential pair 7 and a resistor 8. The resistor couples a DUT to the output 9 of the buffer amplifier and a collector of one of the differential pair's transistors is also coupled to the DUT. A level-controlling signal can then be applied to the input 10 of the buffer amplifier and a data signal (e.g., a digital signal) applied to the differential control terminals 11 of the differential pair. In response to the data signal, the differential pair steers the current 12 of a programmable current source 13 to and away from the collector that is coupled to the DUT. Thus, the level of the signal applied to the DUT can be controlled with the level-controlling signal and its amplitude controlled with the programmed current of the current source.
Although this latter pin driver circuit facilitates the automatic control required in ATEs and is much simpler and accordingly less expensive than the first and second exemplary pin drivers, its generated waveforms depart from the desired symmetry and amplitude. For example, FIG. 1B illustrates a typical waveform 14. The differential pair of the pin driver pulls the programmed current across the resistor (8 in FIG. 1A) and, accordingly, the falling edge 15 of the waveform 14 is steep and linear as it descends to the lower waveform level 16. There is a pronounced overshoot 17, however, as the falling edge transitions to the lower level 16.
In addition, the rising waveform edge 18 exhibits an exponential characteristic as it returns to the upper level 19 of the waveform 14. The rising waveform is generated when the differential pair steers the programmed current away from the resistor. Current to bring the waveform to the upper level 19 is then limited by the resistor (8 in FIG. 1A), and the exponential shape results as this current charges stray circuit capacitance (e.g., collector capacitance of the differential pair).
It is anticipated that the depth of the lower waveform level 16 is given by the product of the steered current (12 in FIG. 1A) and the resistance of the resistor. It has been observed, however, that the lower level typically assumes an error level 16E that differs from the anticipated level 16. The error level is generated because the output impedance of the amplifier (6 in FIG. 1A) typically has a nonzero value and current flow across this impedance adds an additional error term. Furthermore, this error term has a nonlinear characteristic, making it difficult to correct with conventional system calibration techniques.
Because the performance of modern electronic circuits is constantly increasing, there is a demand for test circuits that can generate waveforms whose precision is superior to that of the waveform 14. In addition to applying test waveforms to DUTs, modern ATEs are also generally required to verify that the DUT can sink or source specified pin currents and to verify that the DUT provides specified response waveforms. To provide these functions at each DUT lead, the respective ATE pin electronics preferably includes a waveform driver, an active load and a comparator.